BBU智能化硬件开发工程师
Core
Lead hardware architecture design for 5G/5.5G/6G BBU systems, focusing on high-speed Serdes, DDR memory, power integrity, and thermal reliability to support next-generation base station platforms.
Role type
Senior IC hardware engineer (high-speed base station architecture)
Builds
High-bandwidth, high-reliability BBU hardware platforms for 5G-A/6G base stations
Domain
Telecommunications / High-speed digital hardware
Required skills
High-speed Serdes (112G/224G PAM4) design, DDR4/LPDDR5X hardware design, SI/PI simulation and debugging, Power integrity (PI) and noise analysis, Thermal design and power budgeting, EMC/EMI compliance, PCB layout and stack-up optimization, Oscilloscope and spectrum analyzer usage
Preferred skills
Experience with 5G-A/6G hardware evolution trends, OIF CEI protocol knowledge, Advanced thermal modeling and aging reliability design
Technologies
Serdes, DDR4/LPDDR4X/LPDDR5X, DC-DC/LDO, PCB, EMC, SI/PI simulation tools
Responsibilities
Define BBU hardware architecture and technical roadmaps; Simulate and debug high-speed differential links and memory interfaces; Design power distribution networks and thermal management systems; Resolve EMC/EMI issues and lead mass production validation; Build and maintain hardware design and simulation standards
Seniority
Senior, hands-on IC
