Silicon Engineer
Core
Develops and debugs UVM-based or Formal verification environments for Fabric Interconnect components to ensure design quality and find bugs.
Role type
Senior IC silicon verification engineer
Builds
Verification environments, test plans, and simulations for fabric interconnect components
Domain
Semiconductor hardware verification
Required skills
UVM, System Verilog, Python, random-stimulus generation, coverage-driven verification, formal verification, debugging, test plan development, IP verification, protocol knowledge (CHI, AMBA)
Preferred skills
Generative AI application, scripting, mentorship
Technologies
UVM, System Verilog, Python, CHI, AMBA
Responsibilities
Develop UVM-based or Formal verification environments; run and debug simulations; apply random-stimulus and coverage-based techniques to find bugs; innovate verification methodologies; coach and mentor others; define verification strategies and test plans with partner teams.
Seniority
Senior, hands-on IC
