Experienced ESD Engineer (m/f/d)
Core
Define ESD methodology and design protection circuits to ensure silicon meets Apple's ESD specifications and manufacturing requirements.
Role type
Senior IC ESD Engineer
Builds
High quality on-chip IPs immune to ESD/EOS and latchup events
Domain
Semiconductor / IC Design
Required skills
ESD methodology definition, ESD protection circuit design, test structure development, design rule creation, foundry collaboration, ESD library management, testing plan generation, sign-off review management, debug activities
Preferred skills
Transistor device characteristics, ESD testing models (HBM, CDM, MM, IEC-61000-4-2), ESD circuit design topologies, EDA tools (Virtuoso, Calibre, Allegro), ESD checking tools (PERC, Pathfinder), Si processes for high voltage/RF/ASICs, ESD/LUP test equipment
Technologies
Virtuoso, Calibre, Allegro, PERC, Pathfinder
Responsibilities
Define ESD methodology for all silicon, Design ESD protection devices and circuits, Develop test structures to characterize Si, Develop design rules based on Si characterization, Collaborate with foundry on ESD library and rule development, Maintain ESD device library, Generate or review ESD/LUP testing plans, Manage sign-off reviews, Drive ESD/LUP related debug activities
Seniority
Senior, hands-on IC
