RFIC Layout Engineer
Core
Design transistor-level layouts for RF and analog circuit blocks within wireless SoCs, ensuring high performance and energy efficiency.
Role type
Senior IC RF layout engineer
Builds
Wireless silicon products (SoCs) for consumer devices
Domain
Semiconductor / RF/Analog IC design
Required skills
Deep sub-micron CMOS layout (16nm and lower), FinFet technology, LNA/mixer/PLL/PA/ADC/DAC layout, DRC/LVS/DFM verification, electromigration analysis, signal coupling management, CADENCE tools, RC delay understanding
Preferred skills
Device matching techniques, parasitic minimization, RF shielding, high-frequency routing, guard rings/DNW/PN junctions, process effects (LOD/WPE), CALIBRE scripting, Perl/SKILL scripting, top-level integration leadership
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