RFIC Layout Engineer
Core
Designing transistor-level layouts for RF and analog circuit blocks within wireless System-on-Chip (SoC) products.
Role type
Senior IC RFIC Layout Engineer
Builds
Wireless silicon products (RF/Analog SoCs)
Domain
Semiconductor / Wireless Communications
Required skills
Transistor-level layout, LNA/mixers/PLL/PA/ADC-DAC design, DRC/LVS/DFM verification, floorplanning, power/gnd routing, electromigration analysis, signal coupling mitigation, differential/IQ matching, FinFet technology (16nm and lower), CADENCE tools, CALIBRE interpretation, RC delay understanding, guard rings/DNW/PN junctions
Preferred skills
Device matching techniques, parasitic minimization, RF shielding, high-frequency routing, custom RF/analog layout for transceivers, Perl/SKILL scripting, top-level integration leadership
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