RTL Design Engineer
Core
Specifying, designing, verifying, and supporting lab bring-up of sophisticated digital and mixed-signal circuits.
Role type
Senior RTL Design Engineer (mixed-signal)
Builds
High-performance mixed-signal and analog IPs integrated into high-speed digital circuits
Domain
Semiconductor / Mixed-signal silicon design
Required skills
RTL coding (Verilog, SystemVerilog), mixed-signal circuit design, analog circuit behavioral modeling, static timing analysis, DFT, low-power design methodologies, scripting (Perl, Python, JSON), GenAI tools for code generation
Preferred skills
Micro-architecture, lab bring-up, assertion writing, CDC/RDC/LEQ/UPF flows, digital signal processing
Technologies
Verilog, SystemVerilog, Perl, Python, JSON, GenAI tools
Responsibilities
Specify and/or micro-architect digital blocks in mixed-signal circuits; write RTL code; participate in design verification and bring-up; write test scripts and analyze lab data
Seniority
Senior, hands-on IC