RFIC Layout Engineer
Core
Design and verify transistor-level and block-level layouts for RF and analog circuit blocks in custom CMOS SoCs.
Role type
Senior IC RFIC layout engineer
Builds
Custom RF/analog IP for complex SoC products
Domain
Wireless communications, RF/analog IC design
Required skills
RF/analog transistor-level layout, deep sub-micron CMOS, CALIBRE DRC/ERC/LVS, FinFET technology, Cadence layout tools
Preferred skills
Device matching, parasitic minimization, RF shielding, high-frequency routing, RC delay, electromigration, guard rings, advanced process effects (LOD, WPE), scripting (PERL/SKILL)
Technologies
Cadence, CALIBRE, FinFET
Responsibilities
Detailed transistor-level layout of RF/analog blocks (LNA, mixers, PLL, PA, ADC/DAC, filters), block-level layout with full verification flow (extraction, DRC, LVS, DFM), floorplanning collaboration, layout review for routing and matching
Seniority
Senior, hands-on IC
