SerDes Design and Validation Engineer
Core
Lead system validation, bring-up, and debug of high-performance mixed-signal SerDes IP for Apple SoCs.
Role type
Senior IC analog/mixed-signal validation engineer
Builds
High-speed SerDes PHY blocks (receivers, transmitters, clock networks) for Apple consumer products
Domain
Consumer electronics, high-speed analog/mixed-signal IC design
Required skills
SerDes system bring-up and validation, analog DFT development, mixed-signal verification, high-speed serial link protocols (PCIe, USB, DP, MPHY), Tx/Rx equalization (CTLE, DFE, de-emphasis), CDR architectures, lab and production test debugging, data analysis, analog mixed-signal circuit design fundamentals
Preferred skills
Scripting and automation, firmware-assisted mixed-signal IP development, AI/ML concepts for silicon performance or productivity improvements, layout supervision, bench evaluation, correlation, and characterization
Technologies
PCIe, USB, DP, MPHY, CTLE, DFE, CDR, ATE
Responsibilities
Own SerDes system bring-up, validation, and debug in system environment; define DFT needs to enhance testability; perform mixed-signal verification to understand SerDes operation and interaction with control logic
Seniority
Senior, hands-on IC