SIPI Architect for High-Speed SerDes
Core
Define and own end-to-end signal and power integrity (SIPI) architecture and strategy for cutting-edge high-speed SerDes interconnects, ensuring robust performance from silicon to system.
Role type
Senior IC SIPI Architect (High-Speed SerDes)
Builds
Robust interconnect solutions for high-performance systems
Domain
Semiconductor / High-Speed Interconnects / System-Level Co-Design
Required skills
End-to-end SIPI architecture, System-level trade-off analysis, Statistical and time-domain simulation, SerDes TX/RX equalization, Cross-functional technical leadership, Channel modeling and link budget analysis
Preferred skills
Advanced packaging (2.5D/3D, CPO), System-level power integrity (PDN) and thermal co-design, Data center/HPC interconnect design, Emerging interconnect technologies (Ethernet, PCIe, UAL, CXL), Silicon correlation expertise
