Experienced AMS Analog Layout Engineer (f/m/d)
Core
Senior Analog Layout Engineer responsible for translating design concepts into silicon for custom analog macros and IOs in Apple's SOC flow.
Role type
Senior IC Analog Layout Engineer
Builds
Custom analog macros, IOs, and Mixed-Signal IP for System-on-Chip (SOC) products
Domain
Semiconductor / Analog Mixed-Signal Design
Required skills
Deep submicron CMOS circuit expertise, FinFET technology experience, SKILL/Perl/TCL/Shell/Python scripting, Analog layout design (matching, low noise, low power), DFM best practices, Custom and standard cell-based floor-planning, Hierarchical layout assembly, Physical verification (DRC, ERC, LVS), Cadence Virtuoso (XL, EAD, APR, Constraint Manager), IR drop/RC delay/electromigration/self-heating/coupling capacitance analysis
Preferred skills
Mixed-Signal and RF Integrated Circuits knowledge, Cadence Innovus, CAD Automation, PCell creation
Technologies
Cadence Virtuoso, Cadence Innovus, SKILL, Perl, TCL, Shell, Python
Responsibilities
Craft sophisticated layouts for mixed-signal and analog circuits, Review floorplans, Analyze intricate circuits with circuit designers, Run complete sets of design verification tools, Plan/schedule work and coordinate layout tradeoffs, Interpret LVS, DRC, and ERC reports to optimize layout completion
Seniority
Senior, hands-on IC
