AMS SerDes Robustness Analysis Validation Architect
Core
Architect and execute margin-to-fail validation strategies for high-speed SerDes PHYs (PCIe, USB) to uncover design weaknesses and stress-to-fail conditions across PVT and real-world scenarios.
Role type
Senior IC validation architect (SerDes/Analog)
Builds
High-speed SerDes IP (PCIe, USB, Ethernet, DisplayPort) and system-level integration
Domain
Semiconductor hardware design, high-speed serial links, analog/mixed-signal
Required skills
SerDes design and validation principles, SOC/system integration, margin-to-fail methodologies, stress-to-fail techniques, design-for-testability, silicon behavior analysis, root-cause analysis, test coverage optimization, analog/mixed-signal design, signal integrity, power integrity, high-speed serial protocols, equalization techniques, Python/C++ programming
Preferred skills
PhD in Electrical Engineering, hands-on lab instrumentation (oscilloscopes, BERTs, protocol analyzers), fault injection, internal monitors, behavioral hooks, multi-lane PHY validation, production/characterization flows
Technologies
PCIe, USB, Ethernet, DisplayPort, CTLE, DFE, FFE, Python, C/C++