Analog Layout Automation Engineer (f/m/d)
Core
Convert design concepts into silicon by creating high-performance analog and mixed-signal layouts for next-generation SOCs using AI/ML-driven automation.
Role type
Senior IC analog layout automation engineer
Builds
Multi-billion transistor SOCs for iPhones, iPads, and Macs
Domain
Semiconductor / Analog Mixed-Signal (AMS) / AI for EDA
Deliverable
production ML models
Required skills
Analog/Mixed-Signal layout design, Deep-submicron CMOS/FinFET, Scripting (SKILL, Perl, TCL, Python), AI/ML (CNNs, PyTorch), Physical verification (DRC/ERC/LVS), Floor planning, PCell creation
Preferred skills
Layout automation workflows, Image processing fundamentals, Reliability analysis (IR drop, electromigration), Cadence Virtuoso/Innovus expertise
Technologies
PyTorch, Cadence Virtuoso (XL, EAD, APR), Cadence Innovus, SKILL, Perl, TCL, Shell
Responsibilities
Review floor plans and analyze circuits, Run verification suites and resolve LVS/DRC/ERC issues, Develop scripts to automate layout tasks and quality checks, Apply AI/ML for layout optimization and verification acceleration, Create high-quality analog layouts with tight device matching and low power, Diagnose and resolve layout-related issues
Seniority
Senior, hands-on IC