Analog Layout Automation Engineer
Core
Convert design concepts into silicon by creating high-performance analog and mixed-signal layouts for multi-billion transistor SOCs, leveraging AI/ML for automation and optimization.
Role type
Senior IC analog layout automation engineer
Builds
Next-generation System-on-Chip (SOC) analog/mixed-signal circuits
Domain
Semiconductor design, Analog/Mixed-Signal (AMS), AI/ML for EDA
Deliverable
production ML models
Required skills
Analog/Mixed-Signal layout design, Deep-submicron CMOS/FinFET, SKILL/Perl/TCL/Python scripting, PyTorch, CNNs, DRC/LVS/ERC verification, Floor planning, Physical verification
Preferred skills
AI/ML model development, Image processing fundamentals, DFM best practices, Cadence Virtuoso/Innovus expertise
Technologies
PyTorch, Cadence Virtuoso, Cadence Innovus, SKILL, Perl, TCL, Shell, Python
Responsibilities
Create high-performance analog and mixed-signal layouts, Develop scripts to automate layout tasks and verification flows, Apply AI/ML techniques for layout optimization and quality metrics, Resolve LVS/DRC/ERC issues, Collaborate with circuit designers on floor plans and circuit analysis
Seniority
Senior, hands-on IC