PLL Design Engineer
Core
Designing cutting-edge frequency synthesizers for Compute, SoC, SerDes, and Cellular technologies.
Role type
PLL Design Engineer
Builds
High-quality, innovative hard IPs for Apple's SOC/PHY designs
Domain
Analog-Mixed/Signal, Semiconductor
Required skills
PLL/FLL and frequency synthesis architecture, DCO/VCO design (RO and LC), Fractional-N, SSC, Spur and Jitter cancellation, band gaps, bias circuits, op-amps, LDOs, feedback and compensation, clocking fundamentals, phase noise and jitter analysis, System Verilog modeling
Preferred skills
RTL design and debugging, scripting, industry-standard design tools
Technologies
System Verilog, RO, LC, Fractional-N, SSC
Responsibilities
Develop frequency synthesizers for various applications, perform behavioral simulations to explore architectural performance, design and debug RTL
Seniority
Entry-level, hands-on IC