Mixed-Signal Behavioral Modeling Engineer
Core
Translating custom mixed-signal circuit schematics into efficient SystemVerilog behavioral models for high-level simulations.
Role type
Mixed-signal behavioral modeling engineer
Builds
SystemVerilog behavioral models for analog and high-speed digital circuits
Domain
Semiconductor chip design (mixed-signal)
Required skills
SystemVerilog, circuit schematic reading, logic and behavioral simulations, scripting (Perl/Python)
Preferred skills
Digital logic gates, clocking, state elements, analog blocks (amplifiers, ADCs/DACs, comparators), SPICE simulations, timing synchronous digital logic, PLLs/DLLs/SERDES, digital signal processing, numerical analysis, probability and statistics
Technologies
SystemVerilog, SPICE, Perl, Python
Responsibilities
Translate custom mixed-signal circuit schematics into SystemVerilog behavioral models; interact with circuit design and design verification teams; run simulations and formal equivalence tools; code targeted checks within representative models; write scripts and tools for automating tasks
Seniority
Entry-level, hands-on IC