FE RTL Infrastructure - CAD Engineer
Core
Design and maintain infrastructure, version control, and generative AI solutions for RTL design and verification teams to support Apple Silicon chip development.
Role type
Senior IC infrastructure engineer (RTL/CAD)
Builds
Centralized configuration management systems, version control ecosystems, and generative AI tools for RTL flows
Domain
Semiconductor / Hardware Design Automation
Deliverable
infrastructure
Required skills
Python, Perl, Verilog, SystemVerilog, Perforce administration, centralized configuration management, generative AI development
Preferred skills
Front-End EDA tools (Clock Domain Crossing, Reset Domain Crossing, Lint), RTL build/construction flows, large-scale software system development
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