Digital Layout Design Engineer
Core
Designing complex custom digital layouts, macros, and libraries for state-of-the-art ASICs and microprocessors in deep SubMicron CMOS technologies.
Role type
Senior IC digital layout design engineer
Builds
Custom digital macros, libraries, and SOC components for Apple's silicon products
Domain
Semiconductor / ASIC Design / Physical Design
Required skills
Deep SubMicron CMOS layout design, floorplanning, standard cell planning, hierarchical layout assembly, LVS/DRC/ERC analysis, CAD tool proficiency (Cadence/Mentor), circuit design collaboration
Preferred skills
Layout automation, scripting (CSH/PERL/SKILL), memory compiler development, low noise/low power datapath design, RC delay/electromigration/cross capacitance optimization
Technologies
Cadence, Mentor Graphics, CALIBRE, CSH, PERL, SKILL
Responsibilities
Design complex custom layouts for digital circuits, review and analyze floorplans with circuit designers, run layout verification tools, negotiate layout tradeoffs, interpret LVS/DRC/ERC reports, ensure robust physical design representation
Seniority
Senior, hands-on IC
