Digital Layout Design Engineer
Core
Designing complex custom digital macros and libraries for state-of-the-art ASICs in deep SubMicron CMOS technologies.
Role type
Senior IC digital layout engineer
Builds
Custom digital macros, libraries, and PDV clean layouts for microprocessor SoCs
Domain
Semiconductor / ASIC design
Required skills
Deep SubMicron CMOS layout design, floorplanning, standard cell planning, hierarchical layout assembly, LVS/DRC/ERC analysis, CAD tool proficiency (Cadence/Mentor), circuit-design collaboration
Preferred skills
RC delay/electromigration/self-heating/cross-capacitance optimization, failure-prone structure recognition, CALIBRE report interpretation, scripting (CSH/PERL/SKILL), layout automation, memory compiler development, low-noise/low-power datapath design
Technologies
Cadence, Mentor Graphics, CALIBRE, CSH, PERL, SKILL
Responsibilities
Design complex custom layouts for digital circuits, review and analyze floorplans with circuit designers, run layout verification tools, negotiate layout tradeoffs, interpret LVS/DRC/ERC reports to resolve issues, exceed engineering specifications
Seniority
Senior, hands-on IC
