Silicon Validation/Emulation Design Engineer
Core
Pre-silicon hardware validation of Wireless SoCs with custom hardware accelerators and ARM-based sub-systems using Cadence Palladium emulation platforms.
Role type
Senior IC silicon validation/emulation design engineer
Builds
Pre-silicon validated SoC designs and emulation environments
Domain
Semiconductor / Wireless SoC / Hardware Emulation
Required skills
Cadence Palladium emulation, system-level debug, IP-level debug, emulation compile flows, RTL design concepts, SoC architectures, ARM-based subsystems, automation scripting (Python/Tcl/Perl/Shell), performance profiling
Preferred skills
Synopsys ZeBu, wireless SoC applications (Wi-Fi/Bluetooth/cellular), CI/CD integration, version control systems (Git/Perforce)
Technologies
Cadence Palladium, Synopsys ZeBu, Python, Tcl, Perl, Shell, Git, Perforce, AXI, AHB, APB
Responsibilities
Build and maintain Palladium emulation environments including compile flows and memory modeling. Perform system-level and IP-level debug and root cause analysis. Develop automation scripts to improve build efficiency and debug turnaround. Optimize emulation model performance through compile tuning and partitioning. Collaborate with cross-functional teams to support hardware integration and validation milestones.
Seniority
Senior, hands-on IC
