SEG PMU Engineer
Core
Designing and implementing digital IP blocks for Apple's custom mixed-signal integrated circuits, specifically for power conversion and system management.
Role type
Senior IC digital ASIC engineer (mixed-signal)
Builds
Digital IP blocks for power conversion and system management ICs
Domain
Semiconductor / Mixed-signal ASIC design
Required skills
System Verilog, digital ASIC development flows, low power design techniques, power estimation, block-level specification, tapeout readiness tracking, verification planning, lab validation planning
Preferred skills
SoC digital IP development, synthesis and static timing tools, Clock Domain Crossing design and verification
Technologies
System Verilog, power estimation tools, synthesis tools, static timing tools
Responsibilities
Deliver complex digital IP's meeting schedule, area, power, and performance targets; Collaborate in developing precise design specifications for digital control blocks; Implement physical design ready blocks in System Verilog; Collaborate with project leads to track progress and gauge tapeout readiness; Work with DV teams to create verification plans; Work with silicon validation team in developing lab validation and qualification plans