Layout/Mask Designer
Core
Design complex custom layouts for digital circuits in deep SubMicron CMOS technologies, ensuring robust physical design and optimal PPA.
Role type
Senior IC layout/mask designer
Builds
Digital circuit layouts for Apple products
Domain
Semiconductor / VLSI physical design
Required skills
Layout floor-planning, standard cell planning, hierarchical layout assembly, RC delay analysis, electromigration mitigation, self-heating analysis, cross capacitance management, failure-prone structure recognition, PG grid design, IR simulation, CALIBRE DRC/ERC/LVS interpretation, Cadence Virtuoso, low noise/low power data-path design, memory layout design
Preferred skills
N/A
Technologies
Cadence Virtuoso, CALIBRE, IR simulation tools
Responsibilities
Design complex custom layouts for digital circuits in deep SubMicron CMOS technologies; Review and analyze floorplans and complex circuits with circuit designers; Run layout design verification tools on megacells; Interpret LVS, DRC, and ERC reports to optimize layouts; Perform EMIR simulations and apply fixes for robust power delivery; Review peer layouts and provide improvement recommendations.
Seniority
Senior, hands-on IC
