SerDes Micro Architect
Core
Define micro architecture for analog mixed-signal SERDES IPs to enable high power and performance in Apple silicon devices.
Role type
Senior IC analog mixed-signal micro architect
Builds
High-speed SERDES receiver, transmitter, and clocking blocks for Apple silicon
Domain
Consumer electronics / High-speed analog mixed-signal design
Deliverable
production ML models
Required skills
SERDES design, analog and digital circuit review, firmware code review, system bring-up debugging, factory test leadership, signal integrity analysis, adaptation and optimization algorithms, communications and information theory, equalizers, timing recovery, system identification, DSP concepts, mixed-signal modeling (Python/MATLAB/C/C++)
Preferred skills
Leading definition of high-speed SERDES blocks, Machine Learning concepts, firmware or embedded software development
Technologies
Python, MATLAB, C, C++
Responsibilities
Define micro architecture of analog mixed-signal IPs, review firmware and circuit designs, verify performance requirements, lead debug efforts in system bring-up and factory test, collaborate with signal integrity engineers on system requirements
Seniority
Senior, hands-on IC