Layout Engineer
Core
Lead layout engineering for IC projects, balancing area, performance, and schedule while ensuring design closure and quality.
Role type
Senior IC Layout Engineer
Builds
Custom lead-frames, test vehicles, and final IC layouts for production
Domain
Semiconductor manufacturing, IC design, analog and mixed-signal
Required skills
Full chip layout experience, LVS/DRC/ERC debugging, analog and mixed-signal layout techniques, layout parasitics analysis, device physics knowledge, semiconductor fabrication process understanding, Virtuoso XL/Assura/PVS/Voltas tool proficiency, automation/SKILL coding
Preferred skills
Mentorship of junior engineers, process improvement initiatives, rapid tool/process ramp-up
Technologies
Virtuoso XL, Assura, PVS, Voltas, 40nm, 65nm, 90nm, 130nm, 180nm, BiCMOS, BCD
Responsibilities
Frame layout schedules and risk mitigation plans, collaborate with design/packaging/process teams to balance area/performance/schedule, develop custom lead-frames and test vehicles, analyze and close ESD/LU/thermal/EM issues, mentor junior engineers, ensure final layout meets design expectations
Seniority
Senior, hands-on IC