Design Layout Engineer
Core
Design and verify analog, mixed-signal, and custom digital block layouts for high-performance memory and storage solutions (DRAM, HBM) used in AI and high-performance computing.
Role type
Senior IC Layout Design Engineer
Builds
Custom analog/mixed-signal blocks and full-chip integration for DRAM and High Bandwidth Memory
Domain
Semiconductor manufacturing / Memory and Storage / Analog IC Design
Required skills
Analog/mixed-signal custom layout design, LVS/DRC/Antenna verification, Cadence VLE/VXL, Mentor Calibre DRC/LVS, CMOS process knowledge (Planar, FinFET), critical block implementation (PLL, ADC, DAC, LDO, Bandgap, etc.), layout effects analysis (matching, EM, latch-up, IR-drop)
Preferred skills
Tape-out support experience, multi-project layout management, advanced physical verification problem-solving
Technologies
Cadence VLE/VXL, Mentor Calibre
Responsibilities
Build and develop analog, mixed-signal, and custom digital block layouts; Perform layout verification (LVS/DRC/Antenna) and quality checks; Lead planning, scheduling, and execution for block-level layouts; Collaborate with global engineering teams to ensure project success
Seniority
Senior, hands-on IC