Principal Layout Engineer-DPG-LPDDR
Core
Lead full-chip floor planning, integration, physical implementation, signoff, and tape-out execution for complex analog, mixed-signal, memory, and high-speed interface designs.
Role type
Principal Layout Engineer (Memory & High-Speed Interface)
Builds
Full-chip layouts for LPDDR, HBM, NAND, SERDES, PCIe, UCIe, and advanced SoC products.
Domain
Semiconductor manufacturing, Advanced Node Technologies (FinFET/GAA), Memory & Storage
Deliverable
production ML models | product features
Required skills
Full-chip floor planning, Analog & Mixed-Signal Layout, Memory & High-Speed Interface Layout, Physical Verification & Signoff, DRC/LVS/ERC/EMIR closure, Advanced Node Technologies (FinFET/GAA), Python, SKILL, Tcl, AI/ML for design automation
Preferred skills
Experience with Agentic AI, building AI-powered engineering workflows, intelligent design agents
Technologies
Cadence Virtuoso, Calibre, StarRC, Totem
Responsibilities
Lead cross-functional and global teams, mentor engineers, drive technical excellence, define and scale layout methodologies, drive automation initiatives using AI-assisted design and verification
Seniority
Principal, hands-on IC with technical leadership