AI-Assisted Foundation IP Development Intern
Core
Intern supporting the Foundation IP team in developing standard cell and memory compiler IP for edge AI SoCs, utilizing data analysis and ML to optimize characterization and reduce simulation runs.
Role type
Intern, IC hardware engineer (VLSI/ML)
Builds
Standard cell and memory compiler IP for edge AI SoCs
Domain
Semiconductor / Edge AI / Low-power hardware
Deliverable
production ML models
Required skills
Circuit design, IC layout (DRC/LVS), Python, ML (regression, clustering), Data analysis, Characterization flows
Preferred skills
Virtuoso, Calibre, Liberate, Tempus, Low-power IP for edge AI/IoT
Responsibilities
Support circuit design, spice/Monte Carlo simulation and layout of standard cells; Perform layout tasks (placement, routing, DRC/LVS cleanup); Characterize standard cells (timing, power, noise) across PVT corners; Analyze characterization data using Python to find trends and outliers; Build simple predictive models to flag likely failures and reduce simulation runs; Help debug mismatches between simulated and characterized results; Document findings and share with the IP team