Tech Lead, Analog Mixed Signal Layout
Core
Full-custom layout of high-speed SerDes circuits (RX Front-ends, TX Drivers, PLLs, CDRs, ADCs/DACs) for next-generation transceiver IPs targeting TSMC 3nm technology.
Role type
Senior IC Analog Mixed-Signal Layout Engineer
Builds
High-performance analog/mixed-signal transceiver IPs for rack-scale AI infrastructure
Domain
Semiconductor design, advanced process nodes (FinFET, 3nm)
Required skills
Full-custom layout, high-speed SerDes design, parasitic minimization, floorplanning, DRC/LVS/ERC/EM-IR signoff, tapeout release, semiconductor physics, CMOS fabrication, noise isolation, matching constraints
Preferred skills
Experience with Virtuoso Layout Editor, Calibre, PVS, StarRC, Quantus
Technologies
Cadence Virtuoso XL, Calibre, PVS, StarRC, Quantus
Responsibilities
Perform full-custom layout of high-speed SerDes components; Handle layout of high-frequency components with emphasis on parasitic minimization and routing symmetry; Floorplan and assemble top-level analog/mixed-signal blocks; Work closely with circuit designers to understand schematic intent and matching; Ensure high-quality layout practices to meet DRC, LVS, ERC, and EM/IR signoff; Perform layout-versus-schematic (LVS), design rule checks (DRC), and parasitic extraction (PEX); Support post-layout simulation by delivering clean parasitic netlists; Collaborate with physical design and digital implementation teams on analog-digital boundary integration
Seniority
Senior, hands-on IC
