光通信SerDes链路研发专家
Core
Designing and simulating SerDes link architectures for optical communication systems to ensure high-speed data transmission performance and stability.
Role type
Senior IC SerDes link architect (optical communications)
Builds
High-speed optical communication transceivers and link layers
Domain
Optical communications / High-speed digital/analog IC design
Required skills
SerDes link architecture design, Signal Integrity analysis, RTL circuit modeling (Verilog/SystemVerilog), Mixed-signal IC design, Adaptive equalization algorithms (FFE, DFE, CTLE), CDR, Clock offset cancellation, Eye diagram analysis, Jitter analysis, Channel modeling, Ethernet protocols
Preferred skills
Cadence, HyperLynx, Optical communication industry experience
Responsibilities
Define SerDes link architecture schemes, Perform SerDes link simulation and analysis, Assist in high-speed electrical chip selection, Track and research latest SerDes technology developments
