Digital Design And Implementation Engineer
Core
Design and implement Design-of-experiment (DoE) blocks for standard cells and memory test-chips using digital flow to support technology yield development and IP characterization.
Role type
Digital Design and Implementation Engineer (Physical Design)
Builds
Test-chip designs for technology yield development and IP characterization
Domain
Semiconductor manufacturing / Digital Physical Design
Deliverable
production ML models
Required skills
RTL development, synthesis, floorplanning, place and route, physical verification (DRC, LVS, DFM, MAS), static timing analysis, logical equivalence checks
Preferred skills
Verilog, Python, Ticker coding, Synopsys tools (VCS, ICC2), Cadence tools (Genus, Innovus, Virtuoso)
Technologies
VCS, ICC2, Genus, Innovus, Virtuoso
Responsibilities
Develop DoE blocks for standard cells and memory macros; Create and modify RTL iterating parameters for optimal cell utilization; Drive full digital implementation flow; Run physical verification and resolve violations; Perform timing extraction and static timing analysis; Execute logical equivalence checks
Seniority
Mid-level, hands-on IC