Quantum PDK Design Enablement Engineer
Core
Develop, qualify, and deploy DRC, LVS, and PEX rule decks and verification flows for semiconductor Process Design Kits (PDKs) to enable first-time-right product designs.
Role type
Senior IC physical verification and PDK enablement engineer
Builds
Production-quality physical verification and extraction solutions for customer and internal design flows
Domain
Semiconductor manufacturing / Physical Design / EDA
Required skills
DRC/LVS rule development, Parasitic Extraction (PEX), Python/Tcl/Perl scripting, Root-cause analysis, Regression testing, Semiconductor process knowledge, EDA tool proficiency
Preferred skills
AI/ML for rule generation, Siemens Calibre/Synopsys/Cadence tools, PEX technology-file development, Automated regression environments, Cross-functional technical leadership
Technologies
Python, Tcl, Perl, Shell, Siemens Calibre, Synopsys IC Validator, Cadence Pegasus/PVS
Responsibilities
Develop and maintain DRC, LVS, and PEX rule decks; Translate process requirements into verification solutions; Debug complex verification issues; Develop automation and AI/ML methodologies for rule generation and test creation; Optimize verification flows for accuracy and scalability; Lead medium to large projects and mentor staff
Seniority
Senior, hands-on IC with technical leadership
