Senior Reliability PDK and TFM engineer
Core
Define and generate reliability PDK design rules, drive EDA tool/flow enablement, and deliver competitive TFM/IP ecosystems to support design reliability verification and co-optimization of PPA on Intel technology nodes.
Role type
Senior IC reliability engineer (PDK, TFM, DFR)
Builds
Process Design Kits (PDK), Tool/Flow/Methodology (TFM), Foundational IP, and Design for Reliability (DFR) artifacts
Domain
Semiconductor manufacturing, Process Design, Electronic Design Automation (EDA)
Required skills
PDK development and validation, EDA tool and flow development, reliability physics (BTI, HCI, EM, EOS, ESD), design rule generation, benchmarking analysis, circuit/SOC design reliability validation
Preferred skills
AI/programming for design rule and techfile generation, program management, stakeholder management, high-voltage design, aging mechanisms analysis
Technologies
EDA tools, PDK frameworks, reliability verification suites
Responsibilities
Define reliability PDK design rules and collateral, drive EDA tool/flow enablement for reliability verification, perform competitive analysis and benchmarking of technology reliability
Seniority
Senior, hands-on IC
