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Sr Engineer, CVD/DIFF DRAM

Boise, ID - Main Site💼 Full-time🗓 2026-07-31 → 2026-09-29

Core

Lead development of advanced thin-film processes for future DRAM technologies, driving innovations from concept through high-volume manufacturing.

Role type

Senior IC process engineer (thin-film deposition)

Builds

Next-generation DRAM products

Domain

Semiconductor manufacturing / Memory technology

Deliverable

production ML models | product features

Required skills

Thin-film deposition process design, DOE design and analysis, reaction engineering, thermodynamics, transport phenomena, plasma science, statistical process control (SPC), materials and surface characterization (XPS, AFM, XRD, AES, EBSD, SIMS)

Preferred skills

Tool parameter optimization, DRAM/HPCMOS/EUV technology support, AI/ML for engineering workflows

Technologies

XPS, AFM, XRD, AES, EBSD, SIMS

Responsibilities

Translate DRAM product requirements into scalable thin-film process solutions; Develop, optimize, and characterize thin-film deposition processes; Identify and resolve process defects, yield issues, and reliability risks; Design and implement DOE and analyze results; Partner with equipment and materials suppliers to evaluate new tools and chemistries; Develop and monitor quality control plans using SPC techniques.

Seniority

Senior, hands-on IC

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