NAND Design Rule Manager
Core
Lead a team to support development and large-scale production of advanced 3D NAND technologies, ensuring accurate design-rule and PDK results.
Role type
Manager, NAND Design Rule/Process Integration
Builds
3D NAND memory products and design rule sets (PDKs)
Domain
Semiconductor manufacturing, 3D NAND, Process Integration
Required skills
PDK management, Design Rule Check (DRC) execution, semiconductor device physics, VLSI silicon processing, layout database management, test structure development, cross-functional technical coordination, risk communication, continuous improvement in design-rule pathfinding
Preferred skills
Prior leadership experience in R&D for NAND or other memory technologies
Technologies
Cadence Virtuoso, K2View, Mentor Graphics DRC/RVE
Responsibilities
Lead release of design rules and PDK deliverables; coordinate DRC waivers, mask definitions, and mask reviews; own program execution from kickoff through end-of-life; partner with process integration and unit process areas to guide new 3D NAND generations; ensure high quality and documentation for Build Rule Checks; collaborate with yield improvement and defect analysis to identify and resolve process issues; build and evaluate test structures for next-generation devices; define and track sub-milestones within PDK/DBR/TO schedules; drive continuous improvement in design-rule pathfinding
Seniority
Manager, hands-on IC with team leadership