Sr. Staff Performance Tuning Engineer (CPU PMU & Virtualization)
Core
Identify and analyze performance bottlenecks across CPU, memory hierarchy, cache, and interrupt subsystems; optimize system software, applications, and drivers for throughput, latency, and performance determinism.
Role type
Sr. Staff Performance Tuning Engineer (CPU PMU & Virtualization)
Builds
Optimized performance for NIO's smart electric vehicle computing platforms and virtualization stacks
Domain
Automotive computing, CPU microarchitecture, virtualization
Required skills
CPU pipeline and execution engine analysis, memory hierarchy optimization, interrupt architecture expertise, Linux performance tooling (perf, eBPF, ftrace), C/C++ programming, Python scripting, ARM PMUv3 configuration, Top-Down Microarchitecture Analysis (TMA)
Preferred skills
ARM PMUv3 on Cortex-A55/A76/A78 or Neoverse platforms, KVM/QEMU virtualization stack experience, Xen hypervisor knowledge, seL4 or RTOS/hypervisor environments
Technologies
Linux, perf, eBPF, BCC, bpftrace, ftrace, trace-cmd, C, C++, Python, shell scripting, ARM PMUv3, KVM, QEMU, Xen, seL4
Responsibilities
Profile and reduce hypervisor overhead including VM exits and interrupt injection; optimize vCPU placement strategies and IRQ affinity; investigate cross-core and cross-cluster latency issues on ARM-based systems; design and implement custom event sets for workload-specific performance characterization
Seniority
Sr. Staff, hands-on IC
