Senior Silicon Engineer
Core
Lead capture and validation of design intent for digital and mixed-signal blocks, ensuring accurate constraints and seamless integration across front-end and physical design flows.
Role type
Senior Silicon Engineer (Physical Design & Timing)
Builds
Digital and mixed-signal IC blocks
Domain
Semiconductor / Hardware Design
Required skills
Static timing analysis, RTL to Physical Design collateral development, Synthesis and Timing constraints, Power Performance Area (PPA) trade-offs, Tcl scripting, Python programming, Mixed-signal interface timing closure, Design automation (AI, constraint-checking), Flow improvements, Gate-level power analysis/optimization, UPF and power-intent verification, Synthesis tool capabilities and methods for QoR improvement, Project-level tool setup and configuration.
Preferred skills
Experience with industry tools for synthesis, STA, and PD flows (PrimeTime, Genus/DC, Innovus/ICC2), RTL design and design checks (CDC/RDC/VCLP/LINT).
Responsibilities
Lead capture and validation of design intent for digital and mixed-signal blocks, Provide static timing leadership for mixed-signal interfaces, Run, review and debug physical design flows and timing reports, Contribute to design automation including leveraging AI and flow improvements, Partner with RTL, PD, mixed-signal, DFT, and CAD teams to resolve cross-domain issues.
Seniority
Senior, hands-on IC