ASIC Physical Design
1,642 open positions
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Processor ASIC RTL Design Engineer↗ QualcommSan Diego, CA, US $101k–$101ktoday Define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) for high-performance, low-power products.
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Senior Principal/Sr. Director- SoC/Chip Lead Renesas-ElectronicsBengaluru, KA, in 1d End-to-end technical leadership and execution of complex SoC programs from architecture through silicon production.
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IP Application Engineer AlteraPenang 15, Penang, Malaysia 1d Provide expert guidance to customers and field teams in implementing and optimizing FPGA designs, with strong emphasis on video connectivity and high-speed serial interfaces.
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Senior Staff CAD Engineer MarvellSanta Clara, CA, US $128k–$191k1d Develop and maintain leading-edge Place & Route (P&R) flows and add-on tools for next-generation semiconductor design, defining organization-wide design methodology.
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CryoCMOS Digital IC Design engineer, Quantum GlobalFoundriesAustin, US $98k–$98k1d Design and develop digital CMOS circuits, subsystems, and reusable IP for cryogenic CMOS and quantum systems, driving designs from architecture through silicon validation.
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Manager, Chip Design NVIDIAIsrael, Tel Aviv 1d Lead a team of design and verification engineers to develop core units within Switch Silicon chips, handling micro-architecture for RTL and simulation environment planning.
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IC Design Engineer BroadcomUSA-Colorado-Colorado Springs-4420 Arrowswest Drive $144k–$144k1d Digital IC Design Engineer developing high-performance RTL designs for PCIe Switch and Enterprise Storage products to support AI/ML ecosystems and mega datacenters.
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Performance Modelling Engineer↗ SemidynamicsBarcelona, CT, ES 1d Develops performance models and analysis for custom RISC-V silicon to optimize compute-intensive AI and HPC applications.
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SOC Design Engineer IntelMalaysia, Penang 1d Develop and integrate logic designs for System-on-Chip (SoC) projects, including RTL coding, simulation, and IP block integration.
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Staff Physical Design Engineer: CPU Implementation & Flow Automation SiFiveBengaluru, Karnataka, India 1d Developing and perfecting RTL-to-GDS implementation flows for high-performance CPU cores on leading-edge process nodes.
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Senior Principal Digital Design Engineer NxpSophia-Antipolis (Valbonne), FR 1d Lead architectural definition, micro-architecture, and RTL design of complex digital IP blocks and subsystems for next-generation automotive and secure embedded control products.
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UCIe Applications Engineering, Sr Staff↗ SynopsysPorto, P13, PT 2d Senior Applications Engineer providing UCIe IP integration guidance and support for customer ASIC/SoC flows, from configuration to silicon bring-up.
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Senior FPGA Design Engineer UstIndia 3d Porting, adapting, and optimizing complex IP cores (ASIC RTL, System level models, third-party IP) to FPGA targets, managing high-speed protocol integration and advanced timing closure.
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Senior EMIR Engineer SmartSoC Solutions Pvt LtdIndia 3d Senior EMIR Engineer responsible for analyzing electromigration and IR drop issues, driving convergence, and achieving signoff for complex SoC/ASIC designs.
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Senior / Lead / Principal RTL Design Engineer LeadSoc Technologies Pvt LtdBangalore, Karnataka 3d Design complex semiconductor blocks (IP, SoC, CPU/GPU) from microarchitecture specifications through RTL implementation, synthesis, and sign-off.
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Principal Design Engineer - IP Office MicrosoftUnited States, California, Mountain View 3d Lead AI SoC design by selecting, integrating, and validating best-in-class IP components (PLL, DTS, HBM4, Ethernet) for AI accelerators.
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Principal / Senior IC Architect Engineer↗ Search staffing services pte ltdGeylang, S00, SG 4d Define architecture for next-generation automotive semiconductor products (SoCs, processors, graphics engines) balancing performance, power, area, and cost.
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ASIC Logic Design Engineer (Remote)↗ Asic North, Inc.Remote $120k–$120k4d Designing and implementing digital logic architectures and RTL for customer ASIC products.
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?Hardware/Silicon Internship↗ San Jose, CA, US 4d Designing and verifying energy-efficient processor micro-architecture and RTL for production silicon.
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?Hardware/Silicon Internship↗ Austin, TX, US 4d Designing and verifying energy-efficient processor micro-architecture and RTL for production silicon.
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?Hardware/Silicon Internship↗ Pittsburgh, PA, US 4d Designing and verifying energy-efficient processor micro-architecture and RTL for a new general-purpose computer processor.
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Physical Design Methodology Staff Engineer↗ AMDAustin, TX, US 4d Develop and refine physical design methodologies and EDA tool-chains to optimize CPU core Power, Performance, and Area (PPA) targets for high-performance silicon.
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Senior Hardware Engineer - PCB Design HpeBengaluru, Karnātaka, India 4d Lead the development of next-generation routing and switching platforms from concept to production, focusing on high-speed board design, system-level problem solving, and bringing up complex electronic systems.
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Bluespec Design Engineer (Haskell)
MatXMountain View (HQ) or Remote
$160k–$160k4d
Designing performant silicon RTL at the full-chip or subsystem level for high-performance and sustainable GenAI using Bluespec.
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Physical Design Engineer MicronJalisco, México 5d Drive semicustom physical implementation from netlist handoff through tapeout for advanced semiconductor products.
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Staff Engineer, Timing Samsung Electronics3900 N Capital of Texas Hwy, Austin, TX, USA $151k–$151k5d Ensure timing integrity and signoff readiness for next-generation GPU IPs used in premium smartphones and high-performance computing devices.
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ASIC Engineer I, Annapurna Labs, Early Career - 2027↗ Amazon Web ServicesAustin, TX, US $116k–$116k5d Design and implement RTL for digital logic blocks and develop verification environments for custom silicon products like Graviton, Trainium, and Inferentia.
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Digital IC Design Engineering Intern SemtechCAN - Burlington, ON, CA $54k–$54k5d Design RTL blocks and verify digital subsystems for next-generation mixed-signal ICs in data communications and broadcast video product lines.
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Synthesis & STA Engineer -Singapore↗ Picoheart (sg) Pte. Ltd.Outram, S00, SG 5d Perform logic synthesis, timing signoff, and low-power implementation for chip architectures and RTLs within the Silicon Platform Team.
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2027 Intern - SoC Digital Engineer MotorolasolutionsPlantation, FL, US 5d Develop the digital portion of mixed signal ICs for hi-reliability public safety communications systems using CMOS technologies.
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