ASIC Verification Engineering
1,069 open positions
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FY27 Intern - Soft IP Engineering Internship - Canada (12 or 16 months)↗ QualcommOttawa, ON, CA today Intern contributing to the design and verification of ASIC IP blocks and sub-systems for connectivity standards.
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Design Verification Engineer II↗ Silicon LabsSG today Develop and execute verification plans for Wireless MCU SoCs, building SystemVerilog/UVM testbenches and driving functional coverage closure.
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Design Verification Intern Renesas-ElectronicsDuluth, GEORGIA, us today Develop and verify digital sections of leading-edge memory data buffer chips (DDR5, DDR6+) for datacenter AI and cloud computing applications.
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SoC verification JobgetherRemote $0k–$0k1d End-to-end ownership of verification for complex digital design blocks within advanced ASIC projects, focusing on high-performance networking silicon and interconnect technologies.
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ASIC Verification Engineer, Memory Management - New College Grad 2027 NVIDIAUS, NC, Durham $100k–$100k1d Verify the correctness of Memory Management unit designs for NVIDIA's leading GPUs by developing verification infrastructure, testbenches, and coverage plans.
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Graduate Talent (ISCP SoC Front End Team) IntelMalaysia, Penang 1d Design, development, and validation of next-generation System-on-a-Chip (SoC) technologies and proprietary IPs for Intel Client systems.
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Sr. Staff CAD- ASIC Design Verification Agentic Workflow MarvellSanta Clara, CA, US $128k–$191k1d Lead the development of next-generation Agentic AI workflows for ASIC design verification, automating regression analysis, failure triage, and coverage closure.
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Emulation Engineer (2026 New College Graduate) GlobalFoundriesUSA - Texas - Richardson $86k–$86k1d Build and optimize hardware emulation environments for complex CPU, IP, and SoC designs to accelerate functional debug and improve emulation quality.
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Mixed Signal Verification Lead Engineer NxpPune, IN 1d Develop verification strategies, plans, and functional/AMS models for mixed-signal designs to ensure high-quality silicon tape-outs.
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Memory circuit verification Engineer MicronHyderabad - Phoenix Aquila, India 1d Lead verification and end-to-end analysis of sophisticated full-chip gate-level custom designs for advanced low-power memory technologies (DDR5, LPDDR5, DDR6, LPDDR6) operating at high speeds up to 9600MT/s.
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MLA IP Design Verification Engineer, Annapurna Labs
AmazonAustin, Texas, United States
$157k–$157k1d
Design and validation of machine learning hardware in data centers for cloud server platforms.
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GPU Design Verification Engineer↗ Intel CorporationSanta Clara, CA, US $164k–$232k1d Functional verification of graphics logic components (3D graphics, media, display) to ensure designs meet specifications.
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Senior Manager, Design Verification Engineering AnalogdevicesIndia, Bangalore, RMZ 1d Lead end-to-end pre-silicon design verification for complex digital SoCs, microprocessor-based designs, and AI/ML accelerators.
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Senior Engineer - Design Verification SiFiveAhmedabad, India 1d Senior Design Verification Engineer driving verification of a next-generation cache-coherent interconnect subsystem for high-performance SoCs.
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Senior Formal Verification Engineer TechBiz Global GmbHŁomianki, mazowieckie 2d Design scalable formal testbenches and write mathematical properties to ensure the algorithmic and architectural integrity of vector pipeline execution blocks.
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Senior Staff Formal Verification Applications Engineer↗ SynopsysSunnyvale, CA, US $157k–$157k2d Lead formal verification methodology deployment at customer sites, integrating VC Formal into existing flows to close verification gaps and accelerate tapeout.
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ASIC Design Verification Lead↗ Eridu AISaratoga, CA, US 3d Lead verification execution for complex, high-performance networking silicon (ASIC) to ensure functional correctness and tape-out readiness.
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Mixed- Signal Systems and Verification Engineer CadenceBANGALORE, IN 4d Developing and verifying real-numbered behavioral models for analog/RF blocks in SystemVerilog to ensure accurate representation of analog schematics and integration with RTL.
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Design Verification Engineer - Analog Mixed-Signal (AMS) | BCP↗ Texas InstrumentsSanta Clara, CA, US $130k–$130k4d Design Verification Engineer for Analog Mixed-Signal (AMS) battery charger products, defining, designing, and modeling digital cores for battery management devices.
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Principal / Senior IC Verification Engineer↗ Search staffing services pte ltdGeylang, S00, SG 4d Lead functional verification of complex IPs and SoCs for automotive computing platforms.
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ASIC Verification Engineer HpeBengaluru, Karnātaka, India 4d Design, analyze, develop, and evaluate VLSI components and hardware systems, focusing on architecture, logic design, and design verification through software simulation.
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Design Verification Engineer, Silicon↗
GoogleMountain View, CA, US
$138k–$138k4d
Design and verify complex digital design blocks for silicon chips using SystemVerilog and UVM to ensure bug-free functionality before tape-out.
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Ingénieur(e) Vérification SoC F/H Elsys-DesignVallauris-Antibes-Ouest, Grasse 5d Perform block/top-level verification of complex SoCs for future autonomous and connected automotive systems.
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Senior Digital Verification Engineer Bosch-GroupMilano, Lombardia, it $45k–$45k5d Design and develop scalable, reusable verification environments for complex Mixed-Signal and System-on-Chip (SoC) ASICs to ensure product quality and accelerate first silicon bring-up.
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Senior FPGA Verification Engineer CienaOttawa, CA $104k–$104k5d Lead FPGA verification efforts for complex chip-level designs enabling advanced networking solutions.
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Senior Engineer Functional DV↗ Quest GlobalKA, IN 5d Developing comprehensive verification plans, testbenches, and executing functional tests to ensure design compliance and performance for components like CDP, GDP, USB4, PG, and PM.
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Design-for-Test (DFT) Engineer-Singapore↗ Picoheart (sg) Pte. Ltd.Outram, S00, SG 5d Design-for-Test (DFT) engineering for SoC chips, focusing on scan, MBIST, ATPG, boundary scan, and IP test implementation.
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Senior Staff Engineer Samsung ElectronicsSSIR, Angkor West, Bangalore, India 5d Design Verification Engineer responsible for independent ownership of IP Design Verification (DV), creating test plans, building testbenches, and developing DV infrastructure.
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Formal Verification Engineer AppleMunich, Germany 5d Architecting and leading formal verification efforts for System-on-a-chip (SoC) design blocks and IP to prove properties, find bugs, and improve micro-architectures.
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Data Center Silicon Hardware Engineering Intern - BS - 2027 Co-Op↗ Marvell TechnologyOttawa, ON, CA $67k–$89k5d Design, implementation, and verification of digital hardware blocks and subsystems for next-generation AI computing and networking chips.
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