Senior Engineer - Design Verification
Core
Senior Design Verification Engineer driving verification of a next-generation cache-coherent interconnect subsystem for high-performance SoCs.
Role type
Senior IC Design Verification Engineer
Builds
Cache-coherent interconnect subsystems for high-performance System-on-Chips (SoCs)
Domain
Semiconductor / Chip Design / Computer Architecture
Required skills
SystemVerilog, UVM, cache-coherent system architecture, on-chip interconnects, memory-subsystem behavior, verification of ordering and flow-control semantics, test plan creation, testbench development, assertions, coverage analysis, complex debugging
Preferred skills
NoC verification, subsystem integration, high-performance interface protocols (AXI, CHI, ACE, CXL, UCIe), Python scripting, formal verification, emulation/FPGA-assisted debug
Technologies
SystemVerilog, UVM, Python, AXI, CHI, ACE, CXL, UCIe
Responsibilities
Create verification strategies and test plans for coherent interconnect areas; Develop and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models; Verify subsystem behavior across interface boundaries and bridge paths; Define and execute directed and constrained-random tests to expose corner cases; Analyze failures, isolate root cause, and drive fixes; Collaborate with architecture, design, formal, and software teams; Write functional coverage and close coverage holes; Contribute reusable methodology and automation.
Seniority
Senior, hands-on IC
