Senior Formal Verification Engineer
Core
Design scalable formal testbenches and write mathematical properties to ensure the algorithmic and architectural integrity of vector pipeline execution blocks.
Role type
Senior IC formal verification engineer (datapath/arithmetic)
Builds
Formal verification environments for Vector Unit sub-blocks (pipelines, register files, FPU)
Domain
Semiconductor hardware verification / CPU microarchitecture
Required skills
Formal verification, SystemVerilog, SystemVerilog Assertions (SVA), word-level modeling, bit-blasting, algebraic rewriting, proof convergence management, EDA formal tools, Python/Tcl/Bash scripting
Preferred skills
RISC-V Vector Extension compliance, floating-point arithmetic verification, out-of-order execution mechanics, emulation platforms, core/bus interface protocols
Technologies
Cadence JasperGold/DPV, Synopsys VC Formal, Siemens OneSpin
Responsibilities
Design and maintain formal verification environments for Vector Unit sub-blocks; Implement advanced word-level modeling and algebraic rewriting for IEEE-754 floating-point and integer vector arithmetic; Diagnose and resolve proof-convergence failures and state-space explosions; Develop formal environments to prove RISC-V Vector Extension compliance; Collaborate with simulation engineers to define boundaries between simulation and formal verification; Partner with microarchitects to drive formal-friendly design patterns and review SVA.
Seniority
Senior, hands-on IC
