SoC verification
Core
End-to-end ownership of verification for complex digital design blocks within advanced ASIC projects, focusing on high-performance networking silicon and interconnect technologies.
Role type
Senior IC SoC verification engineer
Builds
Verification environments, testbenches, agents, scoreboards, and functional coverage models for ASIC designs
Domain
Semiconductor / ASIC / High-performance networking
Required skills
SystemVerilog, UVM, directed and constrained-random testing, waveform analysis, protocol debugging, regression triage, functional and code coverage methodologies, simulation tools (VCS, Xcelium, Questa)
Preferred skills
UCIe, PCIe, Ethernet protocol expertise
Technologies
SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, Mentor Questa, UCIe, PCIe, Ethernet
Responsibilities
Build and maintain complete verification environments from scratch; Execute directed and constrained-random testing; Debug verification failures and perform root-cause analysis; Drive functional and code coverage closure; Collaborate with engineering teams to align block-level verification with system-level infrastructure; Contribute to high-quality verification sign-off for networking and interconnect ASIC designs
Seniority
Senior, hands-on IC
