Customer Engagement Engineer II
Core
Provide technical support for Cadence's Palladium, Protium, and Virtual Protocol (PDAPP) products by handling customer cases, debugging complex digital designs, and validating R&D fixes.
Role type
Senior IC digital design verification engineer (EDA)
Builds
Production EDA tools and verification environments
Domain
Electronic Design Automation (EDA) / Digital Logic Design
Required skills
Verilog, System Verilog, VHDL, Unix/Linux scripting, logic design, design debug techniques, emulation, UVM, PCIe/USB/Ethernet protocols
Preferred skills
MS in EE/CE, TBA, SVA, SV coverage, Low Power (UPF), Cadence Palladium product experience
Technologies
SFDC, JIRA, Cadence Palladium, TBA, UVM, Verilog, System Verilog, VHDL, ksh, bash, csh
Responsibilities
Handle incoming customer and field AE cases; report tool bugs to R&D and collect test cases; test R&D fixes/patches; track customer metrics and generate quality reports
Seniority
Mid-level, hands-on IC