Sr. Staff CAD- ASIC Design Verification Agentic Workflow
Core
Lead the development of next-generation Agentic AI workflows for ASIC design verification, automating regression analysis, failure triage, and coverage closure.
Role type
Sr. Staff IC CAD/ASIC Design Verification Engineer (AI/Agentic Workflows)
Builds
AI agents that interact with EDA tools, simulation environments, and verification databases; scalable infrastructure for agent orchestration and multi-agent collaboration.
Domain
Semiconductor / ASIC Design Verification / AI Engineering
Deliverable
production ML models
Required skills
SystemVerilog, UVM, Assertions (SVA), Functional Coverage, Constrained-random verification, Simulation-based verification, Formal verification, Emulation/FPGA prototyping, LLMs, Agent frameworks, Prompt engineering, AI workflow orchestration, Multi-agent systems, Autonomous planning and execution, Tool calling and function orchestration
Preferred skills
VCS/Verdi, Xcelium/Jasper, Siemens Questa, Coverage and regression management tools, Scripting languages
Technologies
LLMs, Agent frameworks, EDA tools (VCS/Verdi, Xcelium/Jasper, Siemens Questa)
Responsibilities
Develop and deploy agentic workflows for ASIC verification activities; Automate regression analysis, failure triage, root-cause identification, and coverage closure; Build AI agents that interact with EDA tools, simulation environments, and verification databases; Integrate LLM-based assistants into verification flows; Develop workflows for test generation, assertion generation, UVM code creation, bug analysis, coverage improvement recommendations, and documentation generation; Collaborate with design, DV, CAD, and methodology teams; Measure and improve verification productivity through AI-driven automation; Develop scalable infrastructure for agent orchestration and multi-agent collaboration.
Seniority
Sr. Staff, hands-on IC with strategic impact
