ASIC Verification Engineering
1,069 open positions
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VLSI Engineer Intern HpeSpring, Texas, United States of America $73k–$85k6d Intern role focused on ASIC verification within the VLSI design process, including system integration, circuit design, and verification.
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FPGA Development Tools Engineer AlteraPenang 15, Penang, Malaysia 6d Senior Technical Lead driving development, modeling, and validation of FPGA IP and simulation models within the Altera Quartus Prime ecosystem.
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Security Verification/Validation Engineer Intern, BS - Summer 2027 MarvellChandler, AZ, US $62k–$123k6d Intern evaluating security verification tools and exploring AI assistance for security testing within the semiconductor product development lifecycle.
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Product Validation Engineer II: Hardware Verification Quality Assurance (QA) CadenceBELO HORIZONTE, BR 6d Design and execute software validation/test plans for new features in ATPG/DFT and Fault Emulation tools, debug issues, and improve test coverage for Cadence's proprietary hardware emulation platform.
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Principal Verification Engineer ON SemiconductorBangalore, Karnataka, India 6d Ensure functional correctness, robustness, and quality of cutting-edge semiconductor and SoC designs through comprehensive verification planning, testbench development, and advanced simulation techniques.
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VLSI ENGINEER L4↗ WiproGuadalajara, JAL, MX 6d Develop VLSI systems by defining functionalities, architecture, layout, and implementation for clients.
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Design Verification Engineer AppleCupertino, United States of America 6d Ensuring the quality of System-on-Chip (SOC) designs by developing verification methodologies, test benches, and coverage plans.
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Stage Ingénieur : Génération de VIP et d’assertions pour IP mixtes par agents IA (F/H) NxpToulouse, FR 6d Develop an AI agent to automate the generation of reusable verification components (VIPs, checkers, assertions) for digitally controlled mixed-signal IPs, specifically DC/DC converters.
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Software Engineer II: Hardware Verification R&D↗ Cadence Design SystemsBelo Horizonte, MG, BR 6d Develop a compiler for the STIL language to generate hardware testbenches and work on functional safety solutions for emulation environments.
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Electrical Engineer Renesas-ElectronicsAustin, TEXAS, us 6d Develop, debug, and verify digital designs for advanced digital power ICs in pre and post silicon environments.
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Principal DFT Engineer MicrosoftUnited States, Washington, Redmond 7d Lead DFT strategy and execution across multiple projects, defining architecture (scan, MBIST, JTAG) and managing ATPG to ensure high fault coverage and test efficiency.
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ASIC Verification EEJ 2026 Bosch-Groupbengaluru, in 7d Verification of SoCs, automotive ASICs, and subsystems using Metric-driven Verification (MDV) and Formal Verification methodologies.
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Senior Cell Modeling and Verification Engineer NVIDIAUS, CA, Santa Clara $136k–$136k7d Develop behavioral models and verification for custom mixed-signal design cells used across NVIDIA products.
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Emulation Technical Leader CiscoSan Jose, California, US $214k–$214k7d Architecting pre-silicon emulation roadmap and defining DFT emulation strategy for Silicon One's complex ASICs.
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Senior Core Design Verification Engineer IntelMalaysia, Penang 7d Develop and execute verification plans, test benches, and environments to test CPU microarchitectures, identify design bugs, and ensure performance, power, and efficiency goals are met.
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Staff Engineer, GPU Design Verification (Subsystems) Samsung Electronics3900 N Capital of Texas Hwy, Austin, TX, USA $151k–$151k7d Verification of GPU subsystems for Samsung's next-generation mobile GPU, ensuring functional correctness, performance integrity, and architectural intent.
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Senior Design Verification Engineer Texas InstrumentsBengaluru, Karnataka, India 7d Confirm accuracy of analog and mixed-signal electronic designs and integrated circuits before pattern generation and mask development.
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Emulation Engineer BroadcomUSA-CA San Jose Innovation Drive $69k–$69k7d Pre-silicon verification of networking ASICs using emulation platforms to define test plans and verify chip architecture.
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Sr/ IC Design Engineer (Design Verification)↗ Ethos Search Associates Pte LtdSingapore, S00, SG 7d Develop and review test plans, create constrained-random verification environments, and debug tests for complex DUTs to ensure pre-silicon IP/IC/SOCs meet performance specifications.
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Senior Engineer - CPU Verification (ALU, FPU Formal and Datapath Verification) SiFiveBengaluru, Karnataka, India 7d Own verification planning and execution for ALU, floating-point blocks focusing on formal and datapath verification of CPU cores.
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Design Verification Intern↗ Quadric Pty LtdBurlingame, CA, US $104k–$119k7d Intern supporting the design verification of a next-generation General Purpose Neural Processing Unit (GPNPU) for edge AI devices.
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Digital Verification Engineer AnalogdevicesChina, Beijing, Haidian, Xixiaokou 7d Ensure digital and mixed-signal products behave exactly as specified before silicon using Metric Driven Verification (MDV) flow.
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Security Digital Design Engineer↗ SynopsysPorto, P13, PT 7d Design and verify secure hardware IP cores (Security IP) for automotive, AI, and high-performance computing applications, ensuring threat resilience and functional correctness.
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Senior Staff Emulation Engineer↗ Maxlinear Inc.Kallang, S00, SG 7d Create emulation/FPGA models from RTL designs to enable preSilicon and postSilicon functional validation and software development for complex SoC designs.
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Sr Consultant↗ HCLTechAcrelândia, AC, BR 8d Lead a group of Junior Analysts to deliver projects within timelines by collaborating with internal/external stakeholders.
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Senior Silicon Design Engineer - DFT↗ AMDSingapore, S00, SG 8d Design verification engineer focused on DFT methodologies, scan test patterns, and ATPG for next-gen SERDES IPs and SOCs.
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THW Client Co-op (January 2027 - Rochester, NY) CienaNew York $0k–$0k8d Design and verify digital blocks, cores, and subsystems for ASIC products and FPGA-based validation within the WaveLogic coherent engine chipsets.
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