Principal Verification Engineer
Core
Ensure functional correctness, robustness, and quality of cutting-edge semiconductor and SoC designs through comprehensive verification planning, testbench development, and advanced simulation techniques.
Role type
Principal ASIC/SoC Verification Engineer
Builds
Reusable Verification IP (VIP), scalable testbench architectures, and high-quality verification deliverables for SoC/IP designs.
Domain
Semiconductor / SoC Design / Digital Verification
Required skills
SystemVerilog, UVM, constrained-random verification, coverage-driven verification, GLS, timing verification, power-aware verification (UPF/CPF), Python scripting, ARM-based SoC architectures, AMBA protocols, formal verification, CI/regression automation
Preferred skills
AI/ML techniques for verification (intelligent stimulus generation, failure triage), knowledge of EDA tools (Synopsys, Cadence, Siemens)
Technologies
SystemVerilog, UVM, OVM, Python, Perl, Tcl, C/C++, Verilog, UPF, CPF, AXI, AHB, APB, I2C, SPI, UART
Responsibilities
Develop and execute SoC/IP-level verification plans; Architect and enhance SystemVerilog UVM/OVM-based testbenches; Perform Gate-Level Simulation (GLS) and timing verification; Debug complex SoC-level issues involving multiple clock domains and power states; Collaborate with design, architecture, and firmware teams to drive verification closure.
Seniority
Principal, hands-on IC
