FPGA IP Design and Verification Engineer
Core
Performs functional logic verification of FPGA designs to ensure they meet microarchitecture specifications and uncover bugs before silicon.
Role type
Senior IC FPGA verification engineer
Builds
Verified FPGA IP blocks and system simulation models
Domain
Semiconductor / FPGA design
Required skills
Functional logic verification, HDL languages (VHDL, Verilog, SystemVerilog), Scripting (Tcl, Perl, Python), FPGA tools (Quartus, Vivado), Bug debugging, Verification planning, Technical documentation
Preferred skills
Experience with gate-level simulation, Power-aware simulation, Collaboration with RTL and physical design teams
Responsibilities
Develop FPGA verification plans, test benches, and verification environments; Execute verification plans and run system simulation models; Replicate and debug issues in pre-silicon environments; Collaborate with architects and developers to improve verification of complex features; Maintain and improve functional verification infrastructure and methodology; Document test plans and drive technical reviews
Seniority
Senior, hands-on IC
