Senior EMIR Engineer
Core
Senior EMIR Engineer responsible for analyzing electromigration and IR drop issues, driving convergence, and achieving signoff for complex SoC/ASIC designs.
Role type
Senior IC physical design engineer (power integrity)
Builds
Complex SoC/ASIC designs
Domain
Semiconductor / ASIC Physical Design
Required skills
EMIR analysis and convergence, RedHawk-SC, IR Drop analysis, Electromigration analysis, Power Grid (PG) specification and validation, EMIR debugging and signoff closure, ECO guidance for PnR teams, ASIC Physical Design flows
Preferred skills
Static/Dynamic IR Drop analysis, current-density violation analysis, Multi-Voltage/Multi-Power-Domain design knowledge, UPF/CPF knowledge, Tcl/Python/Perl/Shell scripting, DRC/LVS exposure, STA concepts
Technologies
RedHawk-SC, Power Grid (PG), PnR tools
Responsibilities
Perform EM/IR analysis and signoff for complex SoC/ASIC designs, Analyze Static/Dynamic IR Drop, Electromigration, and current-density violations, Perform root-cause analysis of EMIR violations and identify corrective actions, Validate PnR databases, PG connectivity, power structures, and EMIR inputs, Drive EMIR convergence in collaboration with Physical Design teams, Provide ECO recommendations for PG strengthening, Correlate EMIR issues with placement, routing, power, and timing to identify root causes, Support block and full-chip EMIR signoff closure
Seniority
Senior, hands-on IC
