Physical Design Engineer
Core
Physical IC Design Engineer responsible for taking RTL to silicon tape-out for PCIe Switch and Enterprise Storage products.
Role type
Senior IC physical design engineer
Builds
PCIe Switch and Enterprise Storage chips for data center and AI/ML ecosystems
Domain
Semiconductor / Hardware Design
Deliverable
production ML models
Required skills
Physical Design, Synthesis, Physical Verification, Timing Closure, EM/IR Analysis, Place and Route, Clock Tree Synthesis, Floor-planning and Layout, Flow and Methodology Development, TCL/PERL Scripting, EDA Tools
Preferred skills
top-level STA, custom clock trees, insertion reduction, skew balancing, top-level floorplanning
Responsibilities
Execute physical design, synthesis, verification, and timing closure; setup and synthesize RTL; perform EM/IR analysis; conduct place and route; manage clock tree synthesis; handle floor-planning and layout; develop flow and methodology; collaborate with RTL engineers.
Seniority
Senior, hands-on IC