Sr. Engineer_ChuPei
Core
Physical design implementation for advanced process nodes (7nm to 3nm), covering floorplanning, timing closure, and sign-off.
Role type
Senior Physical Design Engineer
Builds
Integrated circuits and semiconductor chips
Domain
Semiconductor / VLSI Design
Required skills
floorplanning, clock planning, place and route, timing closure, ECO, IR signoff, physical verification, schedule management, flow issue resolution
Responsibilities
Perform floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification; Manage schedule, resolve design and flow issues, drive methodologies and execution
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