Staff/ Sr Staff Engineer, STA
Core
Own RTL-to-Gate conversion, constraint development, and timing closure to deliver high-performance, low-power chips.
Role type
Staff/Senior Staff Backend Design Expert (Static Timing Analysis & Logic Synthesis)
Builds
Optimized gate-level netlists and timing-closed silicon for automotive, industrial, infrastructure, and IoT SoCs/MCUs.
Domain
Semiconductor Design / EDA / Physical Design
Required skills
Static Timing Analysis (STA), Logic Synthesis, PPA optimization, Tcl/Python/Perl scripting, EDA tool expertise, UPF management, Formal Verification (LEC), Multi-mode/Multi-corner analysis
Preferred skills
Mentoring junior engineers, cross-functional collaboration
Technologies
Fusion Compiler, Innovus, Primetime, Tempus, VCLP, LEC, SystemVerilog, SDC, UPF
Responsibilities
Execute hierarchical and physical-aware synthesis flows; perform block-level and full-chip STA across MMMC scenarios; architect and manage SDC/UPF constraints; implement UPF-based low-power architectures; automate flows using scripting to reduce TAT.
Seniority
Senior, hands-on IC
