Senior FPGA Design Engineer
Core
Porting, adapting, and optimizing complex IP cores (ASIC RTL, System level models, third-party IP) to FPGA targets, managing high-speed protocol integration and advanced timing closure.
Role type
Senior IC FPGA design engineer
Builds
Robust FPGA architectures for high-performance systems
Domain
Semiconductor hardware design / Digital logic
Required skills
Verilog, SystemVerilog, VHDL, Xilinx Vivado, Altera Quartus, ModelSim, UVM, static timing analysis (STA), Clock domain crossing (CDC), high-speed serial protocols (PCIe, USB), DDR4/DDR5 memory interfaces
Technologies
Xilinx Vivado, Altera Quartus, ModelSim, VDS
Responsibilities
Migrate ASIC RTL and third-party IP to FPGA fabrics, rewrite or wrapper-engineer RTL for target constraints, ensure strict performance and timing requirements, integrate high-speed protocols
Seniority
Senior, hands-on IC
